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eBook The Verilog® Hardware Description Language epub

by Donald E. Thomas,Philip R. Moorby

eBook The Verilog® Hardware Description Language epub
  • ISBN: 0792395239
  • Author: Donald E. Thomas,Philip R. Moorby
  • Genre: Engineering
  • Subcategory: Engineering
  • Language: English
  • Publisher: Springer; 2nd edition (December 31, 1994)
  • Pages: 296 pages
  • ePUB size: 1668 kb
  • FB2 size 1982 kb
  • Formats azw mobi lrf lrf


I used this book in an upper level hardware design course. The course had a beginning Verilog course as a prerequisite.

I used this book in an upper level hardware design course. I hadn't taken that course but I had experience in digital design and VHDL. Some pluses: -Example designs are short, complete, and simulatable. This is not a hardware design text. My guess is anything on that CD is not as good as industry standard tools like Mentor's ModelSim.

Don Thomas at Carnegie Mellon University, and are adapted here with permission.

Donald E. Thomas, Philip R. Moorby. XVII Acknowledgments CHAPTER 1 Verilog - A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the NAND Latch 4 Module Hleral'Chy 6 The Counter 7 Components of the Counter 9 A Clock for the System 10 Tying the Whole Circuit Together 11 Using An Alternate Description of the Flip Flop 13 Behavioral Modeling 1 S A Behavioral Model of the.

always, Donald E. Thomas Philip R. Moorby March 2002. module binaryToESeg Behavioral. output reg eSeg, input

always, Donald E. output reg eSeg, input.

The book is divided into four sections, any of which would be an excellent reference alone. The first section is a tutorial introduction comprised of one chapter. More advanced topics, essential for any ASIC designer or graduate student are covered in the next section. Some of the topics are behavioral modeling, concurrent processes and switch level modeling.

XVII Acknowledgments CHAPTER 1 Verilog - A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the NAND Latch 4 Module Hleral'Chy 6 The Counter 7 Components of the Counter 9 A Clock for the System 10 Tying the Whole Circuit Together 11 Using An Alternate Description of the Flip Flop 13 Behavioral Modeling 1 S A Behavioral Model of the.

The book is also ready for use in university courses, having been used for .

The book is also ready for use in university courses, having been used for introductory logic design and simulation through advanced VLSI design courses. An appendix with tutorial help and a work-along style is keyed into the introduction for new students. Material supporting a computer-aided design course on the inner working of simulators is also included.

The Verilog hardware description language is widely used in both industry and academia for the description of digital systems. The language supports the early conceptual stages of design with its behavioural level of abstraction and the later implementation stages with its structural level of abstraction. The language provides hierarchical constructs, allowing the designer to control the complexity of description. This work takes a tutorial approach to presenting the language. It starts with a tutorial introduction which presents the major features of the language by example. It then continues with a more complete discussion of the language constructs. Numerous examples are provided to allow the reader to learn by example. Finally, a formal description of the language is provided in the Appendix. Overall, the presentation balances a learn-by-example style with a definitive discussion of the language. It assumes a knowledge of introductory logic design and software programming. As such, the book is of use to practicing integrated circuit design engineers, and undergraduate and graduate electrical or computer engineering students. The tutorial introduction provides enough information for students in an introductory logic design course to make simple use of logic simulation as part of their laboratory experience. The rest of the book could then be used in upper level logic design and architecture courses. Included in the book is a disk that contains a DOS version of the VeriWell Verilog simulator as well as examples from the book. The examples can be simulated, modified and re-simulated. The simulator can also be used to solve the exercises.
Comments: (7)
Anararius
I've been using VHDL for a long time for FPGA designs but now need to move over to Verilog for new projects. So far I've only read through the Introduction chapter but I can already read and write simple demo Verilog code (blinky.v). I only gave it 4 stars since, like all these books, it assumes I'm simulating on a much more detailed level than the standard FPGA simulator. This requires skipping sections and mentally editing out the simulation commands from examples.

I expect the rest of the book will be as good as the intro, I'll update this if anything changes.
Usanner
Like most books on verilog or VHDL, this book barely touches on how to write testbench code.
The RAM example code was quite useful for me.
Bort
This book takes the beginning verilog student through a quick tutorial with exercises for practice as you learn. The book is well written for learning the subjects it presents. The only reason it does not get five stars is because it is not a good reference. The information is in there, however, the index is incomplete and the information is scattered throughout the book. Finding information takes some manual searching. Otherwise, it is one of the best books for learning verilog. I used the included software instead of the Xilinx Foundation Series software for Students. The included software supports the complete verilog set, not just the sythesizable subset. If you are experienced, looking for a good reference , will spend nearly $150 for a book, and do not need a verilog simulator, I recommend the Complete Verilog Book. See my review of that book for more information.
Pad
This book should be used only by the experienced users that can filter out problematic sections.
Major problems:
- first chapter, "recommended" by authors for university courses, is extremely chaotic (begin..end blocks are called loops, exercises ask you to use loops before introducing them, etc.)
- cover of the latest edition claims coverage of the latest Verilog standard - unfortunately it is very poor coverage: new interesting features such as libraries and configurations are not mentioned at all!
- I had to work hard during many trainings to correct bad coding styles showing in students reading this book as their first Verilog publication
- the book is grossly overpriced...
Main advantage:
- good set of examples
Rleillin
'The Verilog Hardware Description Language' is a very good tutorial and reference for intermediate designers.

I used this book in an upper level hardware design course. The course had a beginning Verilog course as a prerequisite. I hadn't taken that course but I had experience in digital design and VHDL. This book got me up to speed quickly with it's many examples and tight explanations of the Verilog Language.

Some pluses:

-Example designs are short, complete, and simulatable. Most are even synthesizable. This is good because an example can be quickly understood in its entirety. You don't need to flip through and stare and multiple pages to get an idea of what's going on. If you insist on having them, there are two long, practical examples towards the end of the book.

-The text is very well written. Similar in style to 'The C Programming Language by Kernighan and Ritchie.'

-Verilog 2001: Focuses on 2001, which is a little clearer than previous standards. I think all tools support 2001 by default now so that should be used.

Some minuses:

-Too expensive.

-Not enough discussion on how Verilog constructs are compiled and netlisted. This is critically important in FPGA/ASIC design. However, this book is not any worse than other HDL books in this respect. It's just so important, I really haven't seen anything that gives the topic the treatment it deserves.

Possible minus:

-Not really for beginners. This is not a hardware design text.

I haven't used the CD that came with the book so I can't comment on that. My guess is anything on that CD is not as good as industry standard tools like Mentor's ModelSim.

Overall a very impressive book that will get you to productivity quickly in a Verilog project.
Whitebeard
I thought this book was great. It covers the verilog language in a way that makes it clear exactly how the simulator works, so you can predict the results of your program with confidence. This book is also very clear as to what hardware will be generated by what constructs. The very important difference between latches and flip-flops is fully covered here, as is a full description of which constructs will generate (probably unwanted) latches. This was my third Verilog book, and this was the only one that left me feeling confident as to the extent of my knowledge. This is the only one you need.

The only shortcoming of this book is that the authors decided not to cover every llittle bit of verilog, which would have removed the need to consult the standard. Since the standard is so unreadable, I think that this was a crying shame, but I don't think that this will pose a real problem for most readers. Besides, I haven't seen a credible alternative.
Ieregr
I really liked the book since I had read a copy from my school library hence I decided to purchase one. Unfortunately since Amazon doesn't set any standards that all sellers should meet, my purchase was a rip off.

I order the book assuming it was a North American Copy Unfortunately The one that I received was printed in CHINA & FULL OF GRAMMATICAL MISTAKES please watch out for the seller "Express_Textbook" do not purchase unless u want a Chinese Version.

The seller does not specify this information so once you have made a transaction you'd have to go through the hassle of returning it.

A NOTE TO AMAZON ADMIN: PLEASE INSIST SELLERS WHEN SELLING NEW PRODUCTS TO SPECIFY DETAILS SO THAT CUSTOMERS CAN MAKE THE RIGHT CHOICE.
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